Forum Discussion
Altera_Forum
Honored Contributor
14 years agoI wouldn't expect a tightly coupled connection to suddenly become the critical timing path moving from SOPCB to Qsys. I suspect the fitter is struggling on different paths and trading off some slack in other places like the tightly coupled connection. Have you constrained all your I/O using .sdc constraints? Also are you seeing only setup timing violations or are there others in your design as well?
If you haven't tried yet there is a pipelining setting called "Limit interconnect pipeline stages to:" on the project settings tab in Qsys. If it's set low (like 0 or 1) perhaps try increasing it to see if that makes a difference for your design.