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Altera_Forum
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16 years ago

Timing problems even though quartus says circuit meets timing requirements

I have a design that works correctly when clocked around 25 MHz (everything is clocked by a single PLL). Quartus's Classic Timing Analyzer gives an "actual time" of 63.24 MHz. If I bump the PLL up ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

In adition to Tricky's recomendations, a few things more you may want to check.

There's usually more than one model per device. Were the timing requirements met for all of the timming models?

Does your input clock have jitter and have you added uncertanty to account for it?

Can the rest of the board cope with 60 MHz and have you properly specified the I/O constraints?