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Altera_Forum's avatar
Altera_Forum
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16 years ago

Timing problems even though quartus says circuit meets timing requirements

I have a design that works correctly when clocked around 25 MHz (everything is clocked by a single PLL). Quartus's Classic Timing Analyzer gives an "actual time" of 63.24 MHz. If I bump the PLL up ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Have you got any logic generated clocks?

How about ansyncronous set/resets?

latches?

The timing analyser can only check register to register timing, It cant cope with any of the above. If you have any of the above, you have a poor design that will cause the problems you describe.