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Altera_Forum's avatar
Altera_Forum
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12 years ago

timing problem with 8051 integration

Hi, I have a serious timing problem in my design. My design includes a 8051 CPU and a SPI protocol. Each design on it's one, allows me a ~130Mhz frequency. For some reason, once...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hard to tell.

Maybe it's due to placement. The more you fill your FPGA, the more you start to have non-optimal routing.