Forum Discussion
Altera_Forum
Honored Contributor
13 years agoYup it is very complex calculation which does depends on the PAR , Fanouts etc.
Although yet another guess but the devinfo folder gives info to the simulator about the quality of the device to be used which includes the fabric quality at different speed grades, the manufacturing defects , the quality of tranveivers and the architecture of the FPGA for placement ie suppose the tool places a LAB at X20_Y11_N1 (just consider) but that a LAB exists in this location and not an M10k or a DSP or an HSSI is provided by some files which is somewhat gathered from devinfo, but yes since i have never been able to open it i cant guarantee of it. :)