Timing issue for divison

Hello there,

I have the following HDL code, which mainly deals with divison.

assign mod_lo_div2 = (mod_lo_div == 32'b0) ? 100 : mod_lo_div;

assign t_pump_low0 = clk_divd_p1 - capped_duty_cycle;

assign t_pump_diff = t_pump_low0_reg / mod_lo_div_reg;

always @(negedge resetn or posedge clk)

begin

if(~resetn) begin

mod_lo_div_reg <= 100;

t_pump_low0_reg <= 0;

t_pump_low1_reg <= 0;

mul_cyc_cnt <= 0;

end

else begin

if(mul_cyc_cnt < 4) mul_cyc_cnt <= mul_cyc_cnt + 1;

else mul_cyc_cnt <= 0;

if(mul_cyc_cnt == 4) begin

mod_lo_div_reg <= mod_lo_div2;

t_pump_low0_reg <= t_pump_low0;

t_pump_low1_reg <= t_pump_low0_reg - t_pump_diff;

end

else begin

mod_lo_div_reg <= mod_lo_div_reg;

t_pump_low0_reg <= t_pump_low0_reg;

t_pump_low1_reg <= t_pump_low1_reg;

end

end

end

The constraints for the above in a SDC file

set_multicycle_path -from [get_clocks {inst|the_cpu_pll|sd1|pll7|clk[2]}] -to [get_pins {inst|the_z_pwm_0|z_pwm_0|task_logic|t_pump_low1_reg*|data*}] -setup -end 4

set_multicycle_path -from [get_clocks {inst|the_cpu_pll|sd1|pll7|clk[2]}] -to [get_pins {inst|the_z_pwm_0|z_pwm_0|task_logic|t_pump_low1_reg*|data*}] -hold -end 1

The timing requirements are not met as shown in an attached file.

Please have a look and give some clue.

Many thanks.