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Altera_Forum
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14 years ago

Timing issue for divison

Hello there, I have the following HDL code, which mainly deals with divison. assign mod_lo_div2 = (mod_lo_div == 32'b0) ? 100 : mod_lo_div; assign t_pump_low0 = clk_divd_p1 - capped_du...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thank you very much indeed. Retry after removing the final else statement, timing requirements are not met. The timing results are attached where the names of some variables are changed from "*low*" to "*lo*".