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Altera_Forum
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12 years ago

Timing constraints for output ports

Hi everyone, I've been puzzled by how to setup a timing constraints for a while now. Current design I am working on is not complicated (as a matter of fact, you may say it's very simple). It's ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Some extra warming message from Quartus II which I don't quite understand

Warning (332009): The launch and latch times for the relationship between source clock: inst5|altpll_component|auto_generated|pll1|clk[0] and destination clock: P4_ext are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.

Also, while I was trying to read relevent information online. I found something called "source-sychronize interfaces". In particular, Altera's website has a page on "Constraining a Center-Aligned Source-Synchronous Output", is that something that I am facing here for my P4 and P5?

On the other hand, Altera AN433 suggested that for Single Data Rate source-synchronize interface, all I have to do is:

set_output_delay -clock [get_clocks output_clk] -max 2 [get_ports data_out]

set_output_delay -clock [get_clocks output_clk] -min -1[get_ports data_out] -add_delay