timing constraints for fpga with external bus interface.

I design my fpga as a device chip. It is connected to ARM in asynchrons external bus which contains signals cs, we, oe, data[0~31], addr[0~24].

I use a high speed clock(in fpga) to synchronous those signals.

cs was selected as a trigger, which has passed through two flip-flop and synchronoused to in-fpga clock domain. it will generate a synchronoused pulse as a trigger. other signal of the interface would be stable when the pulse comes.

my question is how to specific the timing constraints for those pins? how to make sure all of signals be sampled correctly?