Timing constraints for DDR ADC Interface with AD9643

Hi,

I am working on the DDR Interface with the AD9643 ADC from Analog Devices, but I am not able to catch proper signals! May be someone is familiar with 200MHz DDR Interface, here some informations what I've done so far:

FPGA clk: 200MHz

ADC: AD9643 with 200MHz DDR

DCO of ADC is connected to clk_input of FPGA and its clock is from Hardware PLL directly (200MHz)

Timing Diagram of the AD9643 datasheet

https://www.alteraforum.com/forum/attachment.php?attachmentid=9138

Due to the datasheet of the AD9643, the DCO clock is -90° shifted, so I made the follwing constraints:

create_clock -name {FPGA_CLK200} -period 5.000 -waveform { 0.000 2.500 } 
create_clock -name {ADC_DCO} -period 5.000 -waveform { 3.750 6.250 } 

I shift the ADC clock to 270° due to the fact that sdc can't handle negative timing constraints.

In the datasheet the TSKEW is marked with min value of 0.4 and max of 1.0ns, due to that I made the following input constraints:

set_input_delay -clock  -min -0.400  -add_delay
set_input_delay -clock  -max -1.000  -add_delay

The ADC-DCO clock is going to an internal PLL and on that clock I read out the DDR data, but its wrong. According to the datasheet I think it is not necessary to ad 90° phaseshift in the FPGA?

Can someone help me with some ideas? Thanks in advance!