Timing constraints for asynchronous I/O input pin

architecture test of A_filtering is
 
---------------------------------------------------------------
signal adderPulses :std_logic_vector (31 downto 0):= x"00000000";
signal outputSignal :std_logic;
-----------------------------------------------------------------------------
 
begin
		
		
A_filtering : process(inSignal, clock, resetb)
begin 
 
	
		if (resetb = '0') then
		
			adderPulses <= x"00000000";
			outputSignal  <='0';
			
		elsif (clock'event and clock='1') then
			
			if (inSignal ='0') then 
				if(adderPulses > x"00000000")then
						adderPulses <= adderPulses - '1';
				end if;
			elsif (inSignal ='1') then 			
				if(adderPulses < filter)then
						adderPulses <= adderPulses + '1';
				end if;
			end if;	
			
			if (adderPulses =filter)then
				outputSignal<='1';
			elsif (adderPulses =x"00000000")then	
				outputSignal<='0';
			end if;
				
		end if;	
end process A_filtering ;
 
outSignal <= outputSignal;
 
end test;

Hi Ccong1,

Thanks again for your support. Here is the code I was talking about. Do you think is robust to timing constraint?

I've not copied the entity but, both adderPulses and filter are 32-bit std_logic_vector.

Any council or recommendation would be welcome.

In the meantime i will try implementing a double registered input filtering routine.

talk soon.