Timing constraints for asynchronous I/O input pin

Hi Ccong1,

I appreciate very much your answer, i think that could help me a lot.

With "does not reveal the input signal" i would like to emphasize that, sometimes, while one of the 2 FPGAs w same project and same input signal is able to detect the state change of the input signal (i.e. from 0 to 3.3V) the other is not.

I've check in my design and the input signal goes to a channel select port of a 2in multiplexer. Could this cause the undetection of the signal state change?

During debug, I've seen that the output of the filtering instance is stuck @ 0V even if the input signal stay @ 3.3V for several minutes.

I hope I was more clear in the explanation, any further help will be so much appreciated.

thanks all