Timing constraints for ALTLVDS I/O

that help page i quoted is out of date. I was told that there was a change to the Classic Timing Analyzer that might make what the Help page says to do no longer work, so I did a quick check. If I did it correctly, the input maximum delay setting does not work for this purpose anymore. "List Paths" for the reported RSKM still said, "Info: LVDS transmitter channel-to-channel skew is 0.000 ns". It should have listed the external device TCCS that I put in my setting.

If you are using the Classic Timing Analyzer for a design containing an LVDS hard-silicon SERDES receiver, you can manually adjust the reported RSKM values for the TCCS at the FPGA inputs.

if you want rskm to be fully calculated by the tool, then the following procedure might be good enough to keep you from having to convert to TimeQuest for everything just to report RSKM. It worked easily enough for my little test case, but it's more trouble than a manual calculation. If you're starting a new design with an LVDS receiver and care about this, I'd recommend using TimeQuest for everything from the beginning.

Run the Classic Timing Analyzer.

With the project open in Quartus, open TimeQuest.

If TimeQuest doesn't ask for permission to create an .sdc file, run "Constraints --> Generate SDC File from QSF".

Optional step to check your TimeQuest setup: Run "Tasks --> Report RSKM". The values at "Report --> RSKM" should match those in the "RSKM (Receiver Input Skew Margin)" table in the Classic Timing Analyzer report. TimeQuest can do a more detailed analysis than the other analyzer does, so the margins might be slightly better in TimeQuest than in the other analyzer for Stratix III. The margins will be identical for some--I suspect all--other families.

Now you need to add set_input_delay constraints to tell TimeQuest the TCCS of your external transmitter adjusted by your board skew:

• The Quartus on-line help page entitled simply "report_rskm" has an example (find the page using "report_rskm" on the Help Search tab).

• You can use "Constraints --> Set Input Delay" in TimeQuest to do it with a dialog box. In the dialog box, "Clock name" should be the clock associated with the SERDES clock input device pin (it should be in the drop-down list). "Targets" should be the SERDES serial input device pins. These pin names are in the Classic Timing Analyzer "RSKM (Receiver Input Skew Margin)" table.

• I think the absolute magnitude of these constraints doesn't matter, just the difference between them. If you know the delta you want but don't know the "real" max and min magnitudes, just make sure that the delta between the max and min constraints is the skew across your SERDES inputs right at the FPGA input pins (net effect of both the TCCS of the external device and the board skew).

Run "Tasks --> Report RSKM". The margin should be smaller by half the delta between the max and min values you entered for TCCS. (The report_rskm help page says, "RSKM = (TUI - SW - TCCS) /2".)