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The problem (currently) with this method is that there is no way to specify the channel-to-channel skew from an external transmitting device when the Altera FPGA is the receiving device. You will notice that for the receiver, TCCS is reported as 0. This is currently true for both timing analysis engines.
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As Jim's complete post said, TimeQuest has enhancements for this in version 7.1. However, the Classic Timing Analyzer has supported this since years before it became "classic". It's just not obvious because you use a constraint that usually has a different purpose.
From the QII 7.1 on-line help page entitled "Input Maximum Delay timing assignment":
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In designs that use the LVDS I/O standard, you should specify the appropriate Input Maximum Delay to the LVDS receiver megafunction. This input delay should equal the transmitter channel-to-channel skew (TCCS) plus any board skew.
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