Timing constraints for ALTLVDS I/O

FPGA Guy is correct. Let me expand upon this a little however.

First of all, I assume you are talking about timing the ALTLVDS when DPA is not enabled. If DPA is enabled, the clock is centered in the data valid window dyanamically, therefor timing analysis doesn't make sense and cannot be performed.

You cannot use traditional setup/hold analysis on ALTLVDS I/Os. This is not supported in the Classic Timing Analyzer, nor in TimeQuest, nor are there any plans to support this in the future. RSKM analysis must be used instead as FPGA Guy pointed out and showed the formula for.

The problem (currently) with this method is that there is no way to specify the channel-to-channel skew from an external transmitting device when the Altera FPGA is the receiving device. You will notice that for the receiver, TCCS is reported as 0. This is currently true for both timing analysis engines.

The good news is that in the next release of Quartus II software (7.1), TimeQuest will support two new STA Tcl commands, report_rskm (for receivers) and report_tccs (for transmitters). For the recievers, it will use the difference between the set_input_delay -max and the set_input_delay -min constraints as the TCCS value, allowing you to specify the skew on your input data bus. Very cool. For the transmitters, report_tccs will return the transmit channel skew at the output ports.

Jim