Timing constraints for ALTLVDS I/O

hippi_chik,

I am absolutely sure that all of this can be officially be backed through the documentation, but I'll be darned if I'm going to search for it in the 2800 pages of Quartus, and 1300 pages of Cyclone/CycloneII/CycloneIII documentation ;-)

As such, I think that it's usually easier to build a quick stub design and look at the results Quartus gives you. Given that you've built a stub design it'll be quick to compile if you're toying with assignments or alternative logic constructs.