Timing constraints for ALTLVDS I/O

My technique is simple:

For LVDS inputs, first set a Tsu constraint of 0.1ns and compile. Thus will give you Tsu violations on the LVDS pins. Look at the longest actual Tsu delay, and remember it. Then, go back to the Assignment Editor, and change the 0.1ns Tsu constraint to this longest actual delay you just memorized (round up to the nearest 100ps, if you want) and compile again. This makes sure that all Input Delay Chain lengths are set to 0 on all LVDS inputs you have constrained this way.

For LVDS outputs I use the same technique: put a Tco constraint of 0.1ns on the outputs, compile, remember longest Tco delay, then set Tco to this delay (again, round up to 0.1ns) and you should be all set.

Hope this helps,

Ben