Timing constraints for ALTLVDS I/O

Location constraint? You can do that by just setting a location constraint to either one of the differential pins. Quartus will hook up the other half of the differential pair to the complement pin automatically. (Actually, this is evolving a bit. Altera has traditionally treated a differential assignment as any other I/O standard assignment and you never even saw the "two-pins" aspect of this until you got the pinout report. That's changing with recent Quarts versions where a differential I/O buffer primative has been introduced).

If you're asking about constraining in a more general "how do I set this up" sort of sense, then the answer is to run the Megawizard. There are a lot or parameters for the ALTLVDS function and there are enough dependencies and limitations that just calling out the primative in your HDL is asking for trouble. Just run the wizard and instantiate the generated wrapper file in your HDL project.