Timing Constraint help for source sync interface.

If I understood you.

You want the 280 clk as input to PLL which will output 140 clk, data will go to ddrio which will output two parallel streams which will be recombined at 280 inside fabric. Sounds good idea.

I will generate a second clk from pll at 280 zero phase.

I will then take the two streams further into another set of registers (fabric) then combine them and I think this second register set is crucial.

your constraints look ok to me. The rising/falling edge of 140 clk is internal and TQ should take care of it (Idoubt you get failures here but if so then cut path between irrelevant edges such as rising to falling....)

TQ will know the offset of .1 ns relative to 280 clk and that is enough. everything else is internal and known to the tool