Timing Constraint help for source sync interface.

Hi,

I have a source synchronous data input bus running at 280 MHz on a cyclone V. I can't close timing. I can register the inputs using the fast inputs on the IOE, but there is a skew between the clock delay at the IOE vs. the internal fabric that the tools can't reliably close on. I can't get the signal from the IOE to the fabric (the fabric to fabric timing closes). I am attempting to capture the data using the IOE DDR elements as I think I would then have enough margin to get the data off the IOE and into the fabric.

I have:

280 -> PLL / 2 -> 140 MHz clock -> DDR block input clock

I am trying to figure out how to write the timing constraints for proper analysis. There is a 0.1 ns delay from the rising edge of the 280 MHz clock to the data.

I have the following:

derive_pll_clocks -create_base_clocks

derive_clock_uncertainty

set ckper 3.46

create_clock -name inclock -period [expr $ckper] [get_ports {i_clock_in}]

create_clock -name virt_inclock -period [expr $ckper]

set_input_delay -clock virt_inclock 0.1 [get_ports {i_data_in

[*]}]

I am getting a bunch of failures because I think that the timing analyzer is looking at false paths (setup rising to rising, hold rising to falling) based on going through the "Constraining Double Data Rate Source Synchronous Interfaces" tutorial. But that tutorial has the DDR clock at the input pin, not an SDR clock at the input pin.

Any suggestions?