Timing constraint for FIFO megafunction

I am converting a data stream into 10-bit data (simple shift reg) and feeding it into a FIFO. The FIFO is enabled for only 1 clock cycle in every 10, and idle for the 9 cycles in between each load. How do I instruct Quartus that it's ok if it cannot achieve setup/hold at full speed?

edit: solved with multicycle constraints.