timing constraint for clock mux and how to set output delay

Hi Ryan,

I have clkctrl automatically included behind the clock mux by Quartus II in a Cyclone II design. When I do "create_generated_clock" to constrain 2 clocks go through the clock mux, do I need to do another "creat_generated_clock" after the Mux0~clkctrl?

Example,

at the Mux0 output pin:

create_generated_clock -name muxed0_clk-a -source [get_pins {mux39x3:inst102|mux0~0|combout}] -master_clock muxed0~0_clk-a [get_pins {mux39x3:inst102|mux0|combout}]

create_generated_clock -name muxed0_clk-b -source [get_pins {mux39x3:inst102|mux0~0|combout}] -master_clock muxed0~0_clk-b [get_pins {mux39x3:inst102|mux0|combout}] -add

at the Mux0~clkctrl output pin:

create_generated_clock -name clkctrl_clk-a -source [get_pins {inst102|mux0~clkctrl|inclk[0]}] -master_clock muxed0_clk-a [get_pins {inst102|mux0~clkctrl|outclk}]

create_generated_clock -name clkctrl_clk-b -source [get_pins {inst102|mux0~clkctrl|inclk[0]}] -master_clock muxed0_clk-b [get_pins {inst102|mux0~clkctrl|outclk}] -add

Please see the attached screen shot ( technology map viewer)

Thanks,