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Altera_Forum's avatar
Altera_Forum
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11 years ago

Timing and functional simulation results for a ff with asynch set don't match.

Hi

I'm using Quartus 2 13.1 web edition and modelsim altera starter edition 10.1d. I have a terasic D0 board which i run my codes after simulations. My code is like that 


library ieee;
use ieee.std_logic_1164.all;
entity DD is 
port (clk,X :in std_logic; 
        asyncset : in std_logic; -- D'den gelen out1 sinyali 
        Y:out std_logic);
        end entity DD;
architecture behav of DD is
begin
process(clk,asyncset) begin     
    if asyncset = '1' then
        Y<='1';
        elsif rising_edge (clk) then 
        Y<= not X;
end if;
end process;
end architecture behav;

After functional simulation every thing seems ok but when i execute timing simulation it works completely opposite.

Timing Sim

http://www.alteraforum.com/forum/attachment.php?attachmentid=9817&stc=1

Functional Sim

http://www.alteraforum.com/forum/attachment.php?attachmentid=9818&stc=1

What tools should i use to fix this situation? And any advice for this problem ? Thanks.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    This looks like it's working fine to me. The timing simulation will have the propogation delays from the real hardware.

    Also - where is the testbench code? I get the feeling for the functional simulation you havent quite set it up right.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    What should i do to those propogation delays form the real hardware ? They are completely changing behavior of my code. I will use this code as a part of another circuit , and at the begining with the asyncset input set as 0 , my code should produce negatives of X port that is connected to a pushbutton.

    Pushbutton provides a high logic level when depressed.

    http://www.alteraforum.com/forum/attachment.php?attachmentid=9820&stc=1

    But as you see form the timing sim and as i saw form also the terasic D0 board it doesn't work properly.

    As for timing sim. setups ; clk freq. is 50Mhz (20ns) because terasic D0 has a clock signal of 50 Mhz. And i designate other frequencies respect to the main clock. Perid of X is 80ns and asyncset is 320 ns.

    Is it a necessity to write a test bench at least for this simple code?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    What should i do to those propogation delays form the real hardware ? They are completely changing behavior of my code. I will use this code as a part of another circuit , and at the begining with the asyncset input set as 0 , my code should produce negatives of X port that is connected to a pushbutton.

    Pushbutton provides a high logic level when depressed.

    https://www.alteraforum.com/forum/attachment.php?attachmentid=9821

    But as you see form the timing sim and as i saw form also the terasic D0 board it doesn't work properly.

    As for timing sim. setups ; clk freq. is 50Mhz (20ns) because terasic D0 has a clock signal of 50 Mhz. And i designate other frequencies respect to the main clock in order to see all possible inputs and outputs. Period of X is 80 ns and asyncset is 320ns

    Is it a necessity to write a test bench at least for this simple code?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    THose push buttons should be synchronised to the 50 MHz domain. Then there is no problem

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    OK! i see your point , it is already impossible to activate a pushbutton with a period of 80 ns. Even i extend it to 1 us , everything is fixed. thanks.