Timing and functional simulation results for a ff with asynch set don't match.

What should i do to those propogation delays form the real hardware ? They are completely changing behavior of my code. I will use this code as a part of another circuit , and at the begining with the asyncset input set as 0 , my code should produce negatives of X port that is connected to a pushbutton.

Pushbutton provides a high logic level when depressed.

http://www.alteraforum.com/forum/attachment.php?attachmentid=9820&stc=1

But as you see form the timing sim and as i saw form also the terasic D0 board it doesn't work properly.

As for timing sim. setups ; clk freq. is 50Mhz (20ns) because terasic D0 has a clock signal of 50 Mhz. And i designate other frequencies respect to the main clock. Perid of X is 80ns and asyncset is 320 ns.

Is it a necessity to write a test bench at least for this simple code?