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SparkyNZ's avatar
SparkyNZ
Icon for Contributor rankContributor
3 years ago
Solved

Timing Analyzer: Top Failing Paths

Can somebody please help me. I am getting unpredictable behaviour with my design so I have been looking at the Top Failing Paths report. This appears to be full of SignalTap timing issues? What d...
  • SparkyNZ's avatar
    SparkyNZ
    3 years ago

    @sstrell I have a new theory!

    I copied the generated vJTAG module from my Cyclone IV project to the Cyclone V project.

    When creating a new vJTAG module, it asks for the device that it is intended for. Could it be that the one generated for the Cyclone IV is not truly compatible with the Cyclone V?

    I just created a brand new project, added a VJTag and 100Mhz PLL clock same as in the example above: No problems with the timings whatsoever in Top Failing Paths

    So I guess in future I should be regenerating any IP Core components when I move between different FPGA hardware platforms?

SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
3 years ago

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 10/10 survey