Forum Discussion
ContributorTiming Analyzer: Top Failing Paths
@sstrell I have a new theory!
I copied the generated vJTAG module from my Cyclone IV project to the Cyclone V project.
When creating a new vJTAG module, it asks for the device that it is intended for. Could it be that the one generated for the Cyclone IV is not truly compatible with the Cyclone V?
I just created a brand new project, added a VJTag and 100Mhz PLL clock same as in the example above: No problems with the timings whatsoever in Top Failing Paths
So I guess in future I should be regenerating any IP Core components when I move between different FPGA hardware platforms?
Super ContributorSorry, I didn't see that you were using the virtual JTAG IP. I've never used it before so I'm not familiar with how you need to constrain it, but clearly your issue has something to do with it. The user guide makes no mention of anything to put in .sdc.
SparkyNZ@sstrell I have a new theory!
I copied the generated vJTAG module from my Cyclone IV project to the Cyclone V project.
When creating a new vJTAG module, it asks for the device that it is intended for. Could it be that the one generated for the Cyclone IV is not truly compatible with the Cyclone V?
I just created a brand new project, added a VJTag and 100Mhz PLL clock same as in the example above: No problems with the timings whatsoever in Top Failing Paths
So I guess in future I should be regenerating any IP Core components when I move between different FPGA hardware platforms?
