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SparkyNZ's avatar
SparkyNZ
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3 years ago
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Timing Analyzer: Top Failing Paths

Can somebody please help me. I am getting unpredictable behaviour with my design so I have been looking at the Top Failing Paths report. This appears to be full of SignalTap timing issues? What d...
  • SparkyNZ's avatar
    SparkyNZ
    3 years ago

    @sstrell I have a new theory!

    I copied the generated vJTAG module from my Cyclone IV project to the Cyclone V project.

    When creating a new vJTAG module, it asks for the device that it is intended for. Could it be that the one generated for the Cyclone IV is not truly compatible with the Cyclone V?

    I just created a brand new project, added a VJTag and 100Mhz PLL clock same as in the example above: No problems with the timings whatsoever in Top Failing Paths

    So I guess in future I should be regenerating any IP Core components when I move between different FPGA hardware platforms?

SparkyNZ's avatar
SparkyNZ
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3 years ago

@sstrell I just tried removing all tck references in my .sdc file. That is still giving me the same altera_reserved_tck complaints:

I can't remember how the tck entries were put into the .sdc file. I was following some help on adding constraints and I either clicked on "Create Clock" or "Generate Clock" in the Timing Analyzer.

Whereabouts would I find the JTAG constraints template that you refer to? Are you referring to the likes of this:

https://www.intel.com/content/www/us/en/docs/programmable/683081/17-1-1/jtag-signals.html

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf

?

There's about 5 pages worth of .sdc "code" in that section. Would a straight copy and paste of this be enough? I wouldn't have a clue what needs changing in that template "code".

I shouldn't need to add constraints for SignalTap at all should I? The whole reason I ended up here was because my design just stopped working when I added a SignalTap signal monitor.. then when I added another, it started to work again. Whenever I am close to resolving part of what I am working on, the whole thing just stops working - particular around the vJTAG interface.

SparkyNZ's avatar
SparkyNZ
Icon for Contributor rankContributor
3 years ago

@sstrell By pasting in the JTAG template that I found, the tck errors seem to be less:

..but they are still present. I just left the "--customize here--" sections as the defaults.

Is there something else I need to do to get rid of these?

I also re-enabled the SignalTap instance and I now only have the same 3 lines above - so it does look better.

  • SparkyNZ's avatar
    SparkyNZ
    Icon for Contributor rankContributor
    3 years ago

    @sstrell In my efforts to get rid of the above 3 timing errors, I have completely stripped my design right down to nothing.

    module SystemVerilogTest1( input logic  sw1, input  logic clk, output logic clkFast );
  
logic tck, tdi, tdo, cdr, eldr, e2dr, pdr; 
logic sdr, udr, uir, cir, e1dr, bypass_reg;
logic [3:0] ir_in;
logic [3:0] ir_in_copy;
logic ir_out;

vJTAG v(
 .tdo (tdo),
 .tck (tck),
 .tdi (tdi),
 .ir_in(ir_in),
 .ir_out(ir_out),
 .virtual_state_cdr (cdr),
 .virtual_state_e1dr(e1dr),
 .virtual_state_e2dr(e2dr),
 .virtual_state_pdr (pdr),
 .virtual_state_sdr (sdr),
 .virtual_state_udr (udr),
 .virtual_state_uir (uir),
 .virtual_state_cir (cir)
);

always_ff @ (posedge tck) begin
end

Clock100 clock100(
	.inclk0( clk ),
	.c0( clkFast ) );

always_ff @( posedge clkFast )
begin
end

endmodule

    I still have the below problems:

    I have attached my .sdc file too. I must have something wrong in the .sdc file surely?