New Contributor
Super ContributorTo clarify your terminology first, the clock defines the "data required time" for both meeting setup and hold timing requirements.
It appears from your screenshot that the same base clock is used to drive the PLL which in turn clocks both the source register and the destination register in the path you are analyzing.
But you have to remember that there will be clock skew between the clock arriving at the source register and destination register that needs to be taken into account. As such, the entire clock path(s), including its entry on the I/O pin and through the PLL (which performs compensation as noted in the COMP row) must be taken into account for the analysis.
Also, notice that the "latch edge time" in the data required path starts one cycle later (is this a 1GHz clock?) so that has to be taken into account for the data required path.
Seeing the waveform view of this path would help make things clearer.
New ContributorHello,
first of all thank you for your reply!
The analyzed path is using the clock output of the PLL. (250MHz)
Due to the nature of the PLL there will be some jitter.
The Agilex 5 data sheet is defining a 'period jitter for dedicated clock output of 175ps p-p' (max. >100MHz)
For me it seems that the jitter is included in the calculations from line 1 to 16 of the given picture.
The difference for the clock at the end in line 16 is .673 - 0.42 --> 253ps is more than the expected 175ps.
My initial problem is the following.
The Agilex 5 does not support a dedicated LVDS Serdes with 1:6 or 1:7 ratio!
This was surprising for me because Cyclone 10GX and Arria 10 were able to support such things and Agilex 7 too!
My idea was to use the DDRIO to be able to implement the required interface (at least 504MBit ... up to 700MBit).
AN433 is the guide to implement source synchronous interfaces with some hints regarding clocks in the chapter 'input clocks'.
For that reason it seems to be a better approach to use an external clock without the PLL inside the FPGA.
But up to now I was still not able to have a implementaton with a valid timing.
