Timing Analyzer - Delay through a pll

In timing analyzer how does one know the delay from a reference clk input through the pll, clk muxes, etc. to an output pin. I.e. -

[ref clk input pin] --> PLL --> CLK MUX --> [clk out pin]

^

|

[Input CLK] ------------------------+

I want to find the phase shift that output clk will have with reference to the two input clks and pll settings. I thought I knew the answer to this but no.

TIA.