Timing Analysis: express frequency uncertainty of external oscillator

That's not what the set_clock_uncertainty is for.

Refer to the 'timing analyzer set_clock_uncertainty command' (https://www.altera.com/support/support-resources/design-examples/design-software/timinganalyzer/clocking/tq-clock-uncertainty.html) for details.

For your design - assuming a traditional static design consisting of registers and logic - you 'simply' need to constrain it for your faster clock. Providing it runs at 25MHz it'll run quite happily at 20MHz.

You may need to be careful if you use PLLs or other timing related IP.

Cheers,

Alex