Timequest/SDC: How to Constrain Input Data Relative to an Output Clock?

Thanks - I'll do that.

One last question: I'm not very familiar with the tool (or SDC constraints), so forgive me if this is a dumb question: if I create a clock for the output sending the clock off chip, will that reference the clock at the pin, or will it be the internal version of the clock?

To be more specific: I'm generating the k clock from the output of an ALTDDIO_OUT component. There will be a delay through the pad (call it tPAD) and a trace delay (tTRACE) from the FPGA k output pin to the SRAM clock input pin.

Thus if Timequest uses the pin clock as its reference, delay from the clock in the create_generated_clock statement, to the SRAM pin, will be tTRACE; however if Timequest references the internal version of that clock, the total delay to the SRAM input pin would be tPAD + tTRACE.

So is there a way to actually distinguish between the clock on the internal or external side of the pad (or pin)? Or does Timequest simply use one or the other?

I hope I haven't confused the issue - without graphics I'm never sure I'm communicating this clearly.

Thanks,

Chris