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Altera_Forum
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15 years ago

Timequest/SDC: How to Constrain Input Data Relative to an Output Clock?

Hi I am interfacing to a DDR SRAM (not SDRAM), and am clocking read data with a clock generated in the FPGA, rather than a source synchronous echo clock generated by the SRAM. The SRAM i...
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Altera_Forum
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15 years ago

Put a generated clock on the output sending the clock off chip. Use that clock for the -clock option of your set_input_delay constraints. The -max and -min values will be your max and min roundtrip delays.