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Altera_Forum
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15 years ago

Timequest/SDC: How to Constrain Input Data Relative to an Output Clock?

Hi I am interfacing to a DDR SRAM (not SDRAM), and am clocking read data with a clock generated in the FPGA, rather than a source synchronous echo clock generated by the SRAM. The SRAM i...
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Altera_Forum
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15 years ago

Hi Rysc

Thanks for the quick reply. I may not have explained my situation well - I don't have a clock coming back to the FPGA, just data. The input data is clocked in the FPGA by a phase-shifted version of the k output clock.

Thanks,

Chris