Timequest/SDC: How to Constrain Input Data Relative to an Output Clock?

Put a create_generated_clock assignment on the clock being driven by the FPGA(k clock) and it's -source should be whatever drives it, most likely a PLL ouptut.

Put another create_generated_clock assignment on the clock coming back into the FPGA, and it's -source should be the output port k.

Finally, add set_clock_latency assignments to the clock coming back in, with -early and -late values that represent the max and min round-trip delay:

set_clock_latency -source -early 3.2 dqs

set_clock_latency -source -late 5.8 dqs

(I made up the name and numbers).

Your clock coming back in will now trace the whole path around with max and min value.

Now for your set_input_delay constraints, you will probably use the clock going off chip, i.e. k, for the -clock option.