Altera_ForumHonored Contributor13 years agoTimequest(SDC): constraining posedge launch negedge latch Hello guys, How do you contrain a posedge launch register going to a negedge latch register? My circuit contains a series of posedge and negedge driven flops, daisychained. It's function i...Show More
Altera_ForumHonored Contributor13 years agoSo my contraint was OK. Just need to figure out how to fix my code then... Thanks!!!
Recent DiscussionsTiming analysis - long combinational pathAutomatically added negative node for TDS output doesn't work with Agilex 5Quartus 20.1std compilation fails for Quartus map - Device 10AS057K2F40I1SGDuplicate_hierarchy_depth / duplicate_registerQuartusPro 25.3 Crashed after using the Signal Tap Logic Analyzer