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Altera_Forum
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13 years ago

Timequest(SDC): constraining posedge launch negedge latch

Hello guys, How do you contrain a posedge launch register going to a negedge latch register? My circuit contains a series of posedge and negedge driven flops, daisychained. It's function i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

5th attempt in posting code

always @(posedge clk_in) //clk_in runs around 200Mhz

if (reset)

delay_p <= 0;

else

delay_p <= {delay_p[34:0], in};

always @(negedge clk_in)

if (delay_enable)

comp <= compmux;

else

comp <= compmux[3];

always @*

case (delay_register)

0 :compmux <= delay_p[4];

1 :compmux <= delay_p[5];

2 :compmux <= delay_p[6];