Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

TimeQuest(clock skew and data delay varies for a dedicated path)

In my design, it is found that clock skew and data delay are different for a completely identical path when setup and hold slack are checked. Don't understand why. Can somebody help to explain?

I'm using TimeQuest in Quartus II 12.1 to do STA. Device is Cyclone IV EP4CE30F23C6.

Design constraints have been defined in SDC file. Max input delay for data-input pins is set to 1.98ns. Clock is set to 100mhz with 50% duty.

Then, the design was completly compiled. And timequest was used to check setup slack and hold slack for the path from DataIn[7] to data0[7]. The result is as below:

1. Setup check from DataIn[7] to data0[7]

Clock skew = 2.321ns; Data delay = 4.762ns;

2. Hold check from DataIn[7] to data0[7]

Clock skew = 2.41ns; Data delay = 4.122ns;

Setup check and hold check are using completely the same path, but why are clock skew and data delay defferent?

See the attachment for detailed timing report from TimeQuest.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    On-die variation. I talk about it here:

    http://www.alterawiki.com/wiki/timequest_user_guide

    Basically, a given timing model has two sub-models. So, for example, though we're modeling the Slow Corner, it's not like every single path is pegged at that very worst case delay. They could be, but some will be a little faster. (And likewise in the Fast Corner, some paths will be a little faster). Since timing analysis is the comparison of the Data Arrival Path racing to the latch register and needs to either be before(setup) or after(hold) the Data Arrival Path, this variation needs to be accounted for. One other thing to note is that the clock often has common portions between the Data Arrival and Data Required. This will be modeled with the different delays, but then Common Clock Path Pessimism will help timing by the same amount, basically saying there is no on-die variation on the clock tree for the same paths. For I/O, which is what you're showing, this won't happen.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Rysc, Thank you very much. That's exactly the answer and even more than what i want.