TimeQuest(clock skew and data delay varies for a dedicated path)

On-die variation. I talk about it here:

http://www.alterawiki.com/wiki/timequest_user_guide

Basically, a given timing model has two sub-models. So, for example, though we're modeling the Slow Corner, it's not like every single path is pegged at that very worst case delay. They could be, but some will be a little faster. (And likewise in the Fast Corner, some paths will be a little faster). Since timing analysis is the comparison of the Data Arrival Path racing to the latch register and needs to either be before(setup) or after(hold) the Data Arrival Path, this variation needs to be accounted for. One other thing to note is that the clock often has common portions between the Data Arrival and Data Required. This will be modeled with the different delays, but then Common Clock Path Pessimism will help timing by the same amount, basically saying there is no on-die variation on the clock tree for the same paths. For I/O, which is what you're showing, this won't happen.