Forum Discussion
Altera_Forum
Honored Contributor
15 years agoYikes. Good catch. I don't have any examples of source synchronous, and that description is wrong. If the clock were sent off chip from a PLL, then a generated clock should be applied to the output port sending the clock. I will fix that.
I think the two things I want to add near-term are: 1) A longer discussion on general I/O constraints, with examples. 2) A section on source synchronous, with examples. Just hard to find the time. But I will try to change this and upload it shortly, since it is incorrect, and that's the whole benefit of a wiki. Thanks for pointing it out.