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Altera_Forum
Honored Contributor
Honored ContributorTimequest unconstrained paths clock summary
Hello and good morning from Germany. i have got a problem with the timequest Analyser tool. In the following code you can see my first test of the RS232 Interface. It works but if i start the ...
Altera_ForumHonored Contributor
Honored ContributorThis seems a very odd setup. Why are NDATA and l_ready used to asynchronously set the state machine and data bit? thats not very timing safe. They should be part of the logic that flips the design out of the IDLE state. This is the only reason I can think of it's chosen to make the idle state as some form of clock in your async logic.
