rbugalho,
The following is my testing code, which is a very simple one. The function is to do the accumulation of several input data and return the upper 16bit result. Why it fails at 250MHz clock? Cyclone VE should be way fast than that speed. I am a green-hand in using the TimeQuest Time Analyzer. It will be very thankful if you can help me through.
**********************************************************************************
module average
(clock,
reset,
datain,
add_enable,
g_value,
dataout,
data_ready
);
input clock;
input reset;
input [15:0] datain;
input add_enable;
input [15:0] g_value;
output reg [15:0] dataout;
output reg data_ready;
reg [31:0] adder;
reg [7:0] add_counter;
always @ (posedge clock, posedge reset)
begin
if (reset)
begin
adder <= 32'b0;
data_ready <= 1'b0;
end
else
begin
if (add_enable)
begin
data_ready <= 1'b0;
adder <= adder + {16'b0,datain};
end
else
begin
dataout <= adder[31:16];
adder <= 32'b0;
data_ready <= 1'b1;
end
end
end
endmodule