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IDeyn's avatar
IDeyn
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7 years ago

TimeQuest strange behavior - seems like a bug in PLL output clock visualization

Hi all! Recently faced such problem - in the test project there are two PLLs, with input from two base input clocks. One clock is 50 MHz with waveform { 0.000 10.000 } and on also 50 MHz with wavef...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi IDeyn,

The clock you're looking at, divclk, is not directly derived from refclk. Vcoph[0] first derived from refclk. The rise and fall times for vcoph[0] have to be between 1.667 and the period of 3.333, which is why we see the drop in rise time at any refclk offset greater than 3.333. divclk inherits its rise and fall times from vcoph[0], not refclk.

If you want to force divclk to mirror the offset you add to refclk, you can overwrite its waveform with the -offset option as follows:

create_generated_clock -name {ip1_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} -source {ip1_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by XX -multiply_by YY -duty_cycle 50.00 -offset X.XXX { ip1_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk }

Thanks

IDeyn's avatar
IDeyn
Icon for Contributor rankContributor
6 years ago

Hi YY,

I've just tried create_generated_clock command.

I wrote commands WITHOUT -offset option and achieved proper results using Report Clocks command.

Here are exact commands:

create_generated_clock -name {pll1|secpll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} -source {pll1|secpll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} -divide_by 1 -multiply_by 2 -duty_cycle 50.00 -offset 0.000 {pll1|secpll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}

create_generated_clock -name {pll2|secpll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} -source {pll2|secpll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} -divide_by 1 -multiply_by 2 -duty_cycle 50.00 -offset 0.000 {pll2|secpll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}

I attached figure showing that results are right, as expected.

So, the conclusion for me right now is that create_generated_clocks works better than derive_pll_clocks. And it is a potential mislead.

Best regards,

Ivan