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Ok, I've changed the design again. Now I have only rising edge-clocked registers in the entire design, which are loaded when the corrisponding enable signals are active.
The timing simulations are now consistent and the design also meets the timing requirements :)
The conclusions of this thread could be:
- preferably use enabled registers instead of using an asynchronous load signal;
- choose either a rising edge clock or a falling edge one for the design, then let the fitter do the job of avoiding race conditions.
Thank you all for your support.
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number 2 conclusion is the normal practice. However, and this may have misled you, at i/o you are allowed to try and centre align latch clock with data eye. This will reduce setup relationship but is common practice to help an ailing fitter. Do you know why this difference is allowed? Just a short quiz for next week.
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