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Thank for your support.
I think I've got to the point. However I have not understood this method of catching edges. How can be signal_load_old and signal_load be different if before the 'if' statement there is a signal assignment between them?
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What you have to understand is that this is not procedural programming language. The code isn't executed line by line, it is synthesized into a logic circuit. The bit of code above doesn't assign signal_load_old = signal_load and then check if the two are different, it does both at the same time. Essentially it synthesizes to this circuit:
http://www.alteraforum.com/forum/attachment.php?attachmentid=10114&stc=1 Everything in the system is synchronous to the same clock edge, so {do something} will happen at the same time that signal_load_old is clocked in, so there is always an edge detected as shown in the timing diagram in the picture. (I've added some propagation delays in just to highlight better the way it works).
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