TimeQuest slides

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Is the OR gate being used to turn the clock on/off？

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Yes!

The s_ad_sclk_enable is work as a clock enable signal.

s_ad_sclk_enable keep high normally, so that gate clock will output high also.

Something will drive it to low and maintain 16 periods of clk, so that gate clock will output clk signal for 16 periods for reading AD data back. Pls see the following AD Timing diagram:

http://blogimg.chinaunix.net/blog/upfile2/080124091830.jpg

The clk is generated from PLL directly and freq is 12.5MHz.