TimeQuest slides

To your diagram, don't design this way, as it's not synchronous. OUT_AD_SCLK is a clock that drives registers. It is preferable from a synchronous design standpoint to have CLK drive the CLK port of the registers currently driven by OUT_AD_SCLK and have DATA_A drive the clock enable port of those registers. You will have the same functionality, except your clock edges all line up, so you don't have to worry about hold violations and your setup requirements will be based on your clock period. Try to avoid gating clocks as much as possible. (There are conditions where it is required, but they take a lot more expertise, and far too often users gate clocks when they don't need to, which just causes problems later on.)