Timequest reports setup violation in clock "n/a"

You probably did a set_max_delay or set_min_delay assignment on an I/O port. I/O analysis is always analyzed as if there's an external register. (For example, if you do a set_max_delay on an output port of 10ns to try and mimic a 10ns Tco requirement, then TQ treats it like you're driving an external register.) The problem is that TQ doesn't know what clock drives that external register, and ends up calling it n/a.

The constraints intended for I/O constraints are set_input_delay and set_output_delay, which have a -clock parameter, whereby you explicitly tell it what clock is driving the off-chip register.

I know some of the documentation talks about using set_max/min_delay for I/O constraints, and for the most part it's easy and it works. My biggest concern with it is that it ignores PLL phase-shifts. So if you have a set_max_delay of 10ns, and it takes 9ns to get off-chip, then you have a slack of +1ns. Let's say someone else phase-shifts that PLL tap forward by 2ns, so now your data gets out 2ns later. Assuming everything else is the same, the set_max_delay requirement would still say you met timing by 1ns. To account for this, you would need to change the set_max_delay to 8ns, in which case you would fail. This is exactly how set_max/min_delay is supposed to work, and why I don't generally recommend it for I/O, because it's an easy mistake for users to make.