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Altera_Forum
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14 years ago

TimeQuest: report_timing/report_datasheet

I'd like to create a custom report file that analyzes the range of clock-to-output delays on a bus, eg., the minimum clock-to-output, and the maximum, so that I can then inspect the variation, and re...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hey Ryan,

This is likely the longest question you've had to read (see the attached document).

The document and code contains two designs; a synchronous design and an asynchronous SRAM design.

Both designs are analyzed for timing, with some interesting results regarding the VREF pins.

What is still not clear to me, is how to write the 'final' SDC constraints for the SRAM interface. Perhaps you could clarify that for me, and then I'll update the document, and you can add it and the code to your wiki entry.

Cheers,

Dave