Timequest: Q about interconnect delay effect on clock duty cycle

Thanks for the reply. The undesirable result wasn't completely unexpected, I'm reading more documentation to try to get a better understanding of the effects that you had brought up (mainly the 'Guarenteeing Silicon Performance with FPGA Timing Models' paper). Since I'm working with one wire (eliminating crosstalk considerations?) and looking at the fast 850 mV/0 C corner (eliminating supply voltage/temperature variations/silicon speed differences?) I am trying to narrow down what I am looking at in the example (looking at the bullet points in page 3 of the Altera paper as well as the TimeQuest timing reports). The 1 ns difference between the arrival of the clock's rising edge and the arrival of the clock's falling edge along the interconnect is due to rise/fall asymmetry in the switching circuitry across the interconnect? Pessimistic assumptions from process variations?