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Altera_Forum's avatar
Altera_Forum
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13 years ago

Timequest output to extrernal device SDC question

I was attempting to create a SDC file to constrain my outputs but I think I do not understand the case when the FPGA drives an external device with its own clock. For the FPGA inputs I feel like I u...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I have another question. So I added the set_output_delays and create_generated_clock statements, but Quartus/Timequest reports unconstrained paths for setup and hold from clkin1 to clkout1.

Back to the simple schematic attachment, I am passing the clock input to the FPGA to a output pin ungated. So I do not understand these errors:

*Unconstrained input port paths: From:clkin1, To:clkout1

*Unconstrained output port paths: From:clkin1, To:Clkout1

I tried all the various commands like set_max_delay between two clocks but the error persists.